As transistors have decreased in size, the thickness of the silicon dioxide gate dielectric has steadily decreased to increase the gate capacitance and drive current and to raise device performance. As the thickness scales below 2 nm, leakage currents due to tunneling increase drastically, leading to high power consumption and reduced device reliability.
Embedding memory devices in high-κ/metal gate (HK/MG) devices can further miniaturize the combination of the HK/MG devices and the memory devices. However, because the HK/MG devices and the memory devices are formed separately, the associated process needs a lot of masks, which costs a lot. In addition, dummy structure disposed between the HK/MG devices and the memory devices is needed in such process, leading to a waste of space.